Name: Accelerate HPC End-to-end Software and Hardware Design Pipelines
Uploaded: 2023-07-07T15:19:36.217Z
Duration: 49 min 43 s
Description: Learn how disaggregated storage with high performance and capacity-optimized options can enhance the performance of RTL source code and binaries and still keep costs down.

49:43 Seminarios web

Accelerate HPC End-to-end Software and Hardware Design Pipelines

Learn how disaggregated storage with high performance and capacity-optimized options can enhance the performance of RTL source code and binaries and still keep costs down.

This webinar first aired on 14 de junio de 2023

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Pure//Accelerate

HPC workloads, including software development and semiconductor design (EDA), are challenged to meet razor-thin margins and shrink product pipeline cycles. Learn how disaggregated storage with high performance and capacity-optimized options can enhance the performance of RTL source code and binaries and still keep costs down. See how development tools, such as Perforce and JFrog Artifactory, can gain a significant performance and efficiency boost.

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Accelerate HPC End-to-end Software and Hardware Design Pipelines